عنوان ترجمه فایل فارسی: جمع کننده کامل ۱ بیتی زیر آستانه ای در فناوری تراشه هاى نیمه هادى اکسید فلزى تکمیلى۶۵ نانومتری.
عنوان نسخه انگلیسی: ۱-Bit Sub Threshold Full Adders in 65nm CMOS Technology
مرتبط با رشته های : برق و الکترونیک
تعداد صفحات مقاله فارسی: ۱۳ صفحه
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قسمتی از متن انگلیسی:
After this time, in state X, there
is a subthreshold path that sinks a subthreshold current from the output
node, while the right side PMOS transistor tries to hold the state of
the output. To solve this problem we propose an idea to mitigate the
discharging at output node during the state change. To remove the
discharge path during the state change, during the state change, by
applying the B input signal after a delay equals to that of two
inverters, the circuit behavior is improved compared to the original
circuit. As it can be seen from Fig. 6, there are one NMOS transistor
that is in the ON state and one transistor in subthreshold region (VGS=0
and VDS=VDD). As a consequence currents that start to discharge the
state of output node are approximately half of that for the unmodified
circuit. This power reduction has a penalty in area overhead due to the
extra inverter added to the circuit. However since the power consumption
of the proposed circuit is decreased more than 20% the additional area
can be accepted for applications where the power consumption is of main
importance. The noise immunity
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